diff --git a/Src/IACore/inc/IACore/ADT/RingBuffer.hpp b/Src/IACore/inc/IACore/ADT/RingBuffer.hpp
index 3c71632..6848bd6 100644
--- a/Src/IACore/inc/IACore/ADT/RingBuffer.hpp
+++ b/Src/IACore/inc/IACore/ADT/RingBuffer.hpp
@@ -46,6 +46,18 @@ namespace IACore
         // All of the data in ring buffer will be stored as packets
         struct PacketHeader
         {
+            PacketHeader() : ID(0), PayloadSize(0)
+            {
+            }
+
+            PacketHeader(IN UINT16 id) : ID(id), PayloadSize(0)
+            {
+            }
+
+            PacketHeader(IN UINT16 id, IN UINT16 payloadSize) : ID(id), PayloadSize(payloadSize)
+            {
+            }
+
             UINT16 ID{};
             UINT16 PayloadSize{};
         };
@@ -145,9 +157,7 @@ namespace IACore
         UINT32 write = m_controlBlock->Producer.WriteOffset.load(std::memory_order_relaxed);
         UINT32 cap = m_capacity;
 
-        UINT32 freeSpace = (read <= write) 
-            ? (m_capacity - write) + read 
-            : (read - write);
+        UINT32 freeSpace = (read <= write) ? (m_capacity - write) + read : (read - write);
 
         // Ensure to always leave 1 byte empty to prevent Read == Write ambiguity (Wait-Free Ring Buffer standard)
         if (freeSpace <= totalSize)
diff --git a/Src/IACore/inc/IACore/IPC.hpp b/Src/IACore/inc/IACore/IPC.hpp
index 777a40c..331df5a 100644
--- a/Src/IACore/inc/IACore/IPC.hpp
+++ b/Src/IACore/inc/IACore/IPC.hpp
@@ -22,6 +22,8 @@
 
 namespace IACore
 {
+    using IPC_PacketHeader = RingBufferView::PacketHeader;
+
     struct alignas(64) IPC_SharedMemoryLayout
     {
         // =========================================================